I plan to extend RTL model in course project with RISCV_Simulator as the golden model, specifically, adding a cache(MMU) and branch predictor, and develop a co-simulation platform on verilator utilizing DPI-C

Co-simulation

References

COMPUTER ORGANIZATION AND DESIGN RISC-V EDITION

https://github.com/hehao98/RISCV-Simulator
https://github.com/Radioheading/RISC-V-SIMU

Implementation Details

Benchmark Result